diff options
author | Will Deacon <will.deacon@arm.com> | 2015-08-04 18:52:09 +0100 |
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committer | Will Deacon <will.deacon@arm.com> | 2015-08-04 18:52:09 +0100 |
commit | 04b8637be92f284409651088f3856f4290a931d8 (patch) | |
tree | aee6f9d734c0893139664f38d6438e3897dd568b /arch/arm64 | |
parent | 7f08a414f29e7daea661d03231998625257ed3f1 (diff) |
arm64: alternatives: ensure secondary CPUs execute ISB after patching
In order to guarantee that the patched instruction stream is visible to
a CPU, that CPU must execute an isb instruction after any related cache
maintenance has completed.
The instruction patching routines in kernel/insn.c get this right for
things like jump labels and ftrace, but the alternatives patching omits
it entirely leaving secondary cores in a potential limbo between the old
and the new code.
This patch adds an isb following the secondary polling loop in the
altenatives patching.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r-- | arch/arm64/kernel/alternative.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c index fa1d575ab2c2..ab9db0e9818c 100644 --- a/arch/arm64/kernel/alternative.c +++ b/arch/arm64/kernel/alternative.c @@ -132,6 +132,7 @@ static int __apply_alternatives_multi_stop(void *unused) if (smp_processor_id()) { while (!READ_ONCE(patched)) cpu_relax(); + isb(); } else { BUG_ON(patched); __apply_alternatives(®ion); |