summaryrefslogtreecommitdiff
path: root/arch/arm64/mm
diff options
context:
space:
mode:
authorWill Deacon <will.deacon@arm.com>2018-01-29 11:59:57 +0000
committerCatalin Marinas <catalin.marinas@arm.com>2018-02-06 22:53:21 +0000
commitfa0465fc07c2f9f47bd1198ab368d341bd7c7e4e (patch)
tree1015b0bb0f69b0b88e21af1c15924c7102871321 /arch/arm64/mm
parent6dc52b15c4a48052ade2529d639eee401d76e469 (diff)
arm64: assembler: Change order of macro arguments in phys_to_ttbr
Since AArch64 assembly instructions take the destination register as their first operand, do the same thing for the phys_to_ttbr macro. Acked-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm')
-rw-r--r--arch/arm64/mm/proc.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index ab8660eb55ca..cfd22ba9b510 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -153,7 +153,7 @@ ENDPROC(cpu_do_resume)
ENTRY(cpu_do_switch_mm)
mrs x2, ttbr1_el1
mmid x1, x1 // get mm->context.id
- phys_to_ttbr x0, x3
+ phys_to_ttbr x3, x0
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
bfi x3, x1, #48, #16 // set the ASID field in TTBR0
#endif
@@ -169,7 +169,7 @@ ENDPROC(cpu_do_switch_mm)
.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
adrp \tmp1, empty_zero_page
- phys_to_ttbr \tmp1, \tmp2
+ phys_to_ttbr \tmp2, \tmp1
msr ttbr1_el1, \tmp2
isb
tlbi vmalle1
@@ -188,7 +188,7 @@ ENTRY(idmap_cpu_replace_ttbr1)
__idmap_cpu_set_reserved_ttbr1 x1, x3
- phys_to_ttbr x0, x3
+ phys_to_ttbr x3, x0
msr ttbr1_el1, x3
isb