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| author | Catalin Marinas <catalin.marinas@arm.com> | 2020-03-25 11:10:51 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2020-03-25 11:10:51 +0000 |
| commit | 806dc825f01f1543f613b8195112ef06d04eb6d3 (patch) | |
| tree | e239498bc833c3b19b2b27cbdd2fcc6f5d623ed4 /arch/arm64/mm | |
| parent | 0829a076958ddd203cf4824dd330c93ba4662815 (diff) | |
| parent | 6cf9a2dce6bd10cf454cf6299c1c23182cb486e7 (diff) | |
Merge branch 'for-next/asm-cleanups' into for-next/core
* for-next/asm-cleanups:
: Various asm clean-ups (alignment, mov_q vs ldr, .idmap)
arm64: move kimage_vaddr to .rodata
arm64: use mov_q instead of literal ldr
Diffstat (limited to 'arch/arm64/mm')
| -rw-r--r-- | arch/arm64/mm/proc.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 1b871f141eb4..6bd228067ebc 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -411,7 +411,7 @@ SYM_FUNC_START(__cpu_setup) * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for * both user and kernel. */ - ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ + mov_q x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS tcr_clear_errata_bits x10, x9, x5 |