diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2017-06-21 22:45:08 +0100 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2017-07-03 15:24:31 +0200 |
| commit | 88cda00733f0731711c76e535d4972c296ac512e (patch) | |
| tree | e13c890777b9f7bdbad1d2d0746451dfee115932 /arch/arm64/boot/dts | |
| parent | 6ef84a827c37547504514a80bdb35f74a67df5a3 (diff) | |
ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
Contrary to popular belief, PPIs connected to a GICv3 to not have
an affinity field similar to that of GICv2. That is consistent
with the fact that GICv3 is designed to accomodate thousands of
CPUs, and fitting them as a bitmap in a byte is... difficult.
Fixes: adbc3695d9e4 ("arm64: dts: add the Marvell Armada 3700 family and
a development board")
Cc: <stable@vger.kernel.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm64/boot/dts')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index b4d27857c61b..dbcc3d4e2ed5 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -75,14 +75,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; }; soc { |