diff options
| author | Yuantian Tang <andy.tang@nxp.com> | 2018-02-08 15:54:35 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2018-02-24 15:10:02 +0800 |
| commit | 3fd366d8cbb372386c14b7dbf86b05885e04b482 (patch) | |
| tree | 90b584a1618cf7a28650af5a439e6c0ed9e29ffc /arch/arm64/boot/dts | |
| parent | 9b4eefcb70ca79d7dbd3a2a2d29ef9682762eeeb (diff) | |
arm64: dts: ls1043a: add cpu idle support
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 4d15e111cf12..beb3c3500ed6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -81,6 +81,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_PH20>; }; cpu1: cpu@1 { @@ -89,6 +90,7 @@ reg = <0x1>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; }; cpu2: cpu@2 { @@ -97,6 +99,7 @@ reg = <0x2>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; }; cpu3: cpu@3 { @@ -105,6 +108,7 @@ reg = <0x3>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; }; l2: l2-cache { @@ -112,6 +116,23 @@ }; }; + idle-states { + /* + * PSCI node is not added default, U-boot will add missing + * parts if it determines to use PSCI. + */ + entry-method = "arm,psci"; + + CPU_PH20: cpu-ph20 { + compatible = "arm,idle-state"; + idle-state-name = "PH20"; + arm,psci-suspend-param = <0x00010000>; + entry-latency-us = <1000>; + exit-latency-us = <1000>; + min-residency-us = <3000>; + }; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x80000000>; |