diff options
| author | Manish Narani <manish.narani@xilinx.com> | 2018-10-25 11:37:00 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2018-11-06 12:52:49 +0100 |
| commit | e7abd89466df421d22ebda095e00d36976dbdacb (patch) | |
| tree | 366ce4068761fa119ca86e3d55c19c1fd8edccee /arch/arm64/boot/dts/xilinx | |
| parent | 1696acf44e9f26454f15877bee3a9a39ec6e6ee5 (diff) | |
arm64: dts: zynqmp: Add DDRC node
Add ddrc memory controller node in dts. The size mentioned in dts is
0x30000, because we need to access DDR_QOS INTR registers located at
0xFD090208 from this driver.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm64/boot/dts/xilinx')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index dacabde6ff7e..07f2dd13ab33 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -355,6 +355,13 @@ xlnx,bus-width = <64>; }; + mc: memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0x0 0xfd070000 0x0 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; + gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; |