diff options
author | Olof Johansson <olof@lixom.net> | 2015-12-22 12:20:54 -0800 |
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committer | Olof Johansson <olof@lixom.net> | 2015-12-22 12:20:54 -0800 |
commit | 1c5d7957042d034546bdad3161e0578afe8c24ef (patch) | |
tree | add286fd083f8b6c1fe750da3c13303d9ae9160a /arch/arm64/boot/dts/qcom | |
parent | 5b30ffc29d91b9b2cf2e6968f3aab60c97d15384 (diff) | |
parent | 9e1dfb858de43bb3dfbbb32cec57433e9b250dee (diff) |
Merge tag 'qcom-arm64-for-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64
Qualcomm ARM64 Updates for v4.5
* Add fixed rate oscillators to dts
* Fixup PMIC alias and properties
* Change 8916-MTP compatible to be compliant with new scheme
* Fix 8x16 UART pinctrl configuration
* Add SMEM, RPM/SMD, and PM8916 support on MSM8916
* tag 'qcom-arm64-for-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: Add PM8916 support on MSM8916
arm64: dts: qcom: Add RPM/SMD support on MSM8916
arm64: dts: qcom: Add MSM8916 SMEM nodes
arm64: dts: set the default i2c pin drive strength to 16mA
arm64: dts: fix the i2c aliasing to match to schematics.
arm64: dts: qcom: msm8916: Add fixed rate on-board oscillators
arm64: dts: qcom: Alias pm8916 on msm8916 devices
arm64: dts: qcom: Make msm8916-mtp compatible string compliant
arm64: dts: qcom: 8x16: UART1 and UART2 use DMA for RX and TX
arm64: dts: qcom: 8x16: UART1 add CTS_N, RTS_N pin configurations
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm64/boot/dts/qcom')
-rw-r--r-- | arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 2 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 1 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 19 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916.dtsi | 107 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/pm8916.dtsi | 6 |
6 files changed, 128 insertions, 11 deletions
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 14fafa1e9c7c..db17c5d5689c 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -20,6 +20,10 @@ aliases { serial0 = &blsp1_uart2; serial1 = &blsp1_uart1; + usid0 = &pm8916_0; + i2c0 = &blsp_i2c2; + i2c1 = &blsp_i2c6; + i2c3 = &blsp_i2c4; }; chosen { diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index fced77f0fd3a..b0a064d3806b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -17,6 +17,6 @@ / { model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; - compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360", + compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916", "qcom,mtp"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi index a1aa0b201e92..ceeb8a6feed6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi @@ -17,6 +17,7 @@ / { aliases { serial0 = &blsp1_uart2; + usid0 = &pm8916_0; }; chosen { diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 49ec55a37614..955c6f174d4c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -16,10 +16,13 @@ blsp1_uart1_default: blsp1_uart1_default { pinmux { function = "blsp_uart1"; - pins = "gpio0", "gpio1"; + // TX, RX, CTS_N, RTS_N + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; }; pinconf { - pins = "gpio0", "gpio1"; + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; drive-strength = <16>; bias-disable; }; @@ -28,10 +31,12 @@ blsp1_uart1_sleep: blsp1_uart1_sleep { pinmux { function = "gpio"; - pins = "gpio0", "gpio1"; + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; }; pinconf { - pins = "gpio0", "gpio1"; + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; drive-strength = <2>; bias-pull-down; }; @@ -272,7 +277,7 @@ }; pinconf { pins = "gpio6", "gpio7"; - drive-strength = <2>; + drive-strength = <16>; bias-disable = <0>; }; }; @@ -296,7 +301,7 @@ }; pinconf { pins = "gpio14", "gpio15"; - drive-strength = <2>; + drive-strength = <16>; bias-disable = <0>; }; }; @@ -320,7 +325,7 @@ }; pinconf { pins = "gpio22", "gpio23"; - drive-strength = <2>; + drive-strength = <16>; bias-disable = <0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8d184ff19642..915321479998 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -37,6 +37,22 @@ reg = <0 0 0 0>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserve_aligned@86000000 { + reg = <0x0 0x86000000 0x0 0x0300000>; + no-map; + }; + + smem_mem: smem_region@86300000 { + reg = <0x0 0x86300000 0x0 0x0100000>; + no-map; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -74,6 +90,29 @@ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + smem { + compatible = "qcom,smem"; + + memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + hwlocks = <&tcsr_mutex 3>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -103,21 +142,46 @@ reg = <0x1800000 0x80000>; }; + tcsr_mutex_regs: syscon@1905000 { + compatible = "syscon"; + reg = <0x1905000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + }; + + rpm_msg_ram: memory@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x60000 0x8000>; + }; + blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 1>, <&blsp_dma 0>; + dma-names = "rx", "tx"; status = "disabled"; }; + apcs: syscon@b011000 { + compatible = "syscon"; + reg = <0x0b011000 0x1000>; + }; + blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b0000 0x200>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 3>, <&blsp_dma 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -438,6 +502,49 @@ clock-names = "core"; }; }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; + + pm8916-regulators { + compatible = "qcom,rpm-pm8916-regulators"; + + pm8916_s1: s1 {}; + pm8916_s2: s2 {}; + pm8916_s3: s3 {}; + pm8916_s4: s4 {}; + + pm8916_l1: l1 {}; + pm8916_l2: l2 {}; + pm8916_l3: l3 {}; + pm8916_l4: l4 {}; + pm8916_l5: l5 {}; + pm8916_l6: l6 {}; + pm8916_l7: l7 {}; + pm8916_l8: l8 {}; + pm8916_l9: l9 {}; + pm8916_l10: l10 {}; + pm8916_l11: l11 {}; + pm8916_l12: l12 {}; + pm8916_l13: l13 {}; + pm8916_l14: l14 {}; + pm8916_l15: l15 {}; + pm8916_l16: l16 {}; + pm8916_l17: l17 {}; + pm8916_l18: l18 {}; + }; + }; + }; + }; }; #include "msm8916-pins.dtsi" diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index b222ece7e3d2..37432451ee4c 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -4,8 +4,8 @@ &spmi_bus { - usid0: pm8916@0 { - compatible = "qcom,spmi-pmic"; + pm8916_0: pm8916@0 { + compatible = "qcom,pm8916", "qcom,spmi-pmic"; reg = <0x0 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; @@ -90,7 +90,7 @@ }; }; - usid1: pm8916@1 { + pm8916_1: pm8916@1 { compatible = "qcom,spmi-pmic"; reg = <0x1 SPMI_USID>; #address-cells = <1>; |