diff options
| author | Anup Patel <anup.patel@broadcom.com> | 2015-10-02 23:24:18 +0530 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2015-11-16 10:51:53 -0800 |
| commit | 33a93aa490ae256d0b982e2d66cf570cf61f95de (patch) | |
| tree | cff552e20c56172f421a995f8cbae3035729634b /arch/arm64/boot/dts/broadcom/ns2.dtsi | |
| parent | 8005c49d9aea74d382f474ce11afbbc7d7130bec (diff) | |
arm64: dts: Add L2-cache DT node for NS2
Recent kernels requires cache hierrachy to be defined via DT hence
this patch updates NS2 DT accordingly.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Sandeep Tripathy <tripathy@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/broadcom/ns2.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 3c92d92278e5..f7591755c37a 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -50,6 +50,7 @@ reg = <0 0>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; cpu@1 { @@ -58,6 +59,7 @@ reg = <0 1>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; cpu@2 { @@ -66,6 +68,7 @@ reg = <0 2>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; cpu@3 { @@ -74,6 +77,11 @@ reg = <0 3>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; + }; + + CLUSTER0_L2: l2-cache@000 { + compatible = "cache"; }; }; |