diff options
| author | Ben Dooks <ben-linux@fluff.org> | 2008-10-21 14:06:34 +0100 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2008-12-15 21:46:02 +0000 |
| commit | e24b864ab3e1a5916c87e13cfdc94c1d02f0578b (patch) | |
| tree | f2c894494fc6831c72cd980b9d836efa900f5be3 /arch/arm/plat-s3c24xx | |
| parent | 93bc6b6371b6b7303ffdae0d69dcdc443b8b0d8a (diff) | |
[ARM] S3C24XX: Split pll code out of regs-clock.h
Move the PLL calculation code into it's own header
file for re-use with the other plat-s3c24xx based
systems such as the S3C24A0.
Note, we change the name of s3c2410_get_pll to the
more generically named s3c24xx_get_pll as well as
the related defintions.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
| -rw-r--r-- | arch/arm/plat-s3c24xx/clock.c | 3 | ||||
| -rw-r--r-- | arch/arm/plat-s3c24xx/include/plat/pll.h | 37 | ||||
| -rw-r--r-- | arch/arm/plat-s3c24xx/s3c244x.c | 3 |
3 files changed, 41 insertions, 2 deletions
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c index bf2633bd3996..1ff1b9836042 100644 --- a/arch/arm/plat-s3c24xx/clock.c +++ b/arch/arm/plat-s3c24xx/clock.c @@ -49,6 +49,7 @@ #include <plat/clock.h> #include <plat/cpu.h> +#include <plat/pll.h> /* clock information */ @@ -332,7 +333,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, /* initialise the main system clocks */ clk_xtal.rate = xtal; - clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal); + clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), xtal); clk_mpll.rate = fclk; clk_h.rate = hclk; diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h new file mode 100644 index 000000000000..7ea8bffa7a9c --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/pll.h @@ -0,0 +1,37 @@ +/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C24xx - common pll registers and code + */ + +#define S3C24XX_PLLCON_MDIVSHIFT 12 +#define S3C24XX_PLLCON_PDIVSHIFT 4 +#define S3C24XX_PLLCON_SDIVSHIFT 0 +#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) +#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1) +#define S3C24XX_PLLCON_SDIVMASK 3 + +#include <asm/div64.h> + +static inline unsigned int +s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk) +{ + unsigned int mdiv, pdiv, sdiv; + uint64_t fvco; + + mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT; + pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT; + sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT; + + mdiv &= S3C24XX_PLLCON_MDIVMASK; + pdiv &= S3C24XX_PLLCON_PDIVMASK; + sdiv &= S3C24XX_PLLCON_SDIVMASK; + + fvco = (uint64_t)baseclk * (mdiv + 8); + do_div(fvco, (pdiv + 2) << sdiv); + + return (unsigned int)fvco; +} diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c index d1152d1f9ba0..7f33cef20bac 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.c +++ b/arch/arm/plat-s3c24xx/s3c244x.c @@ -42,6 +42,7 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/pm.h> +#include <plat/pll.h> static struct map_desc s3c244x_iodesc[] __initdata = { IODESC_ENT(CLKPWR), @@ -80,7 +81,7 @@ void __init s3c244x_init_clocks(int xtal) /* now we've got our machine bits initialised, work out what * clocks we've got */ - fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; + fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; clkdiv = __raw_readl(S3C2410_CLKDIVN); camdiv = __raw_readl(S3C2440_CAMDIVN); |