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authorJason Wang <jason77.wang@gmail.com>2010-06-12 22:22:39 +0800
committerSascha Hauer <s.hauer@pengutronix.de>2010-07-26 14:18:24 +0200
commit426ab49b3361474622e492cff949853584e3451f (patch)
tree62ae2b90e1b915640f6865cf526002e1a319f0e0 /arch/arm/plat-mxc/include
parentb3fb53a81c73a78f31c3bddb6037adcb7d223ce4 (diff)
mxc/iomux: add GPIO bank offset for iomux v3 platforms
These GPIO bank offsets are useful when define a gpio number. E.G. when GPIO PORTC pin 6 is used for irq request pin of external expanding device, we can define it like: #define EXP_PARENT_IRQ_PIN (GPIO_PORTC + 6) Signed-off-by: Jason Wang <jason77.wang@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc/include')
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d31d5ba..0880a4a1aed1 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -89,6 +89,21 @@ struct pad_desc {
#define PAD_CTL_SRE_FAST (1 << 0)
#define PAD_CTL_SRE_SLOW (0 << 0)
+
+#define MX51_NUM_GPIO_PORT 4
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
+
/*
* setups a single pad in the iomuxer
*/