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authorKirill A. Shutemov <kirill@shutemov.name>2009-09-15 10:23:53 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-09-15 22:06:38 +0100
commit910a17e57ab6cd22b300bde4ce5f633f175c7ccd (patch)
tree2a1dea95ca2d50192216500d90d9b0358af1dc1d /arch/arm/mm/Kconfig
parent59fcf48fdebe65e4774d2c7ec76b7845d281749a (diff)
ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size
Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. It's not true at least for CPUs based on Cortex-A8. List of CPUs with cache line size != 32 should be expanded later. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/Kconfig')
-rw-r--r--arch/arm/mm/Kconfig5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 5fe595aeba69..8d43e58f9244 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -771,3 +771,8 @@ config CACHE_XSC3L2
select OUTER_CACHE
help
This option enables the L2 cache on XScale3.
+
+config ARM_L1_CACHE_SHIFT
+ int
+ default 6 if ARCH_OMAP3
+ default 5