diff options
author | Rabin Vincent <rabin.vincent@stericsson.com> | 2010-10-12 13:00:54 +0000 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2010-10-19 15:17:07 -0700 |
commit | 51f5d744ed07a6b82e5cbbeeabd73605d62dcfc9 (patch) | |
tree | c9e0784f10734280277c3ab96f99917c7431432e /arch/arm/mach-ux500 | |
parent | 4a6aed3c4eb69702335ed3689132d07eabaaf86d (diff) |
ste_dma40: remove enum for endianess
A bool will suffice. The default is little endian.
Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'arch/arm/mach-ux500')
-rw-r--r-- | arch/arm/mach-ux500/devices-db8500.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index d9ceddc22fc2..c04bf2b61dcd 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -135,12 +135,10 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = { .mode = STEDMA40_MODE_PHYSICAL, .dir = STEDMA40_MEM_TO_MEM, - .src_info.endianess = STEDMA40_LITTLE_ENDIAN, .src_info.data_width = STEDMA40_BYTE_WIDTH, .src_info.psize = STEDMA40_PSIZE_PHY_1, .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, .dst_info.data_width = STEDMA40_BYTE_WIDTH, .dst_info.psize = STEDMA40_PSIZE_PHY_1, .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, @@ -149,12 +147,10 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = { struct stedma40_chan_cfg dma40_memcpy_conf_log = { .dir = STEDMA40_MEM_TO_MEM, - .src_info.endianess = STEDMA40_LITTLE_ENDIAN, .src_info.data_width = STEDMA40_BYTE_WIDTH, .src_info.psize = STEDMA40_PSIZE_LOG_1, .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, .dst_info.data_width = STEDMA40_BYTE_WIDTH, .dst_info.psize = STEDMA40_PSIZE_LOG_1, .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, |