diff options
| author | Joseph Lo <josephl@nvidia.com> | 2013-07-03 17:50:39 +0800 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-07-19 10:08:05 -0600 |
| commit | 2f5aaa3d2703256d37ae75818c495783d4ad0543 (patch) | |
| tree | 8a2a04aae10c5fc208e430e7fa4a457190fcfc03 /arch/arm/mach-tegra/reset-handler.S | |
| parent | ac2527bfc21739b77d687df1bfc4e973103fef7b (diff) | |
ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15
When there is a cluster power down cycle in suspend, we need to set up
the correct L2 RAM data RAM latency to make L2 cache work correctly. This
is only needed for cluster 0 and needs to be done in tegra_resume before
the cache is enabled.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/reset-handler.S')
| -rw-r--r-- | arch/arm/mach-tegra/reset-handler.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 75285a3b816e..34614bdf3f5b 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -45,6 +45,7 @@ ENTRY(tegra_resume) check_cpu_part_num 0xc09, r8, r9 bleq v7_invalidate_l1 + blne tegra_init_l2_for_a15 cpu_id r0 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 |