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authorShiraz Hashim <shiraz.hashim@st.com>2011-03-07 05:57:08 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-03-09 09:50:04 +0000
commit981a95d37126cdf09e1dba3884305c2e25375bfb (patch)
tree280cad24a89b16dd91b392b50a6f7c141183c243 /arch/arm/mach-spear3xx/include/mach/spear310.h
parent8fc4ef451eebc72d10c6987b59ec3316da62f02b (diff)
ARM: 6794/1: SPEAr: Append UL to device address macros.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-spear3xx/include/mach/spear310.h')
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h22
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 4f58eb12cc58..1e853479b8cd 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -16,17 +16,17 @@
#ifndef __MACH_SPEAR310_H
#define __MACH_SPEAR310_H
-#define SPEAR310_NAND_BASE 0x40000000
-#define SPEAR310_FSMC_BASE 0x44000000
-#define SPEAR310_UART1_BASE 0xB2000000
-#define SPEAR310_UART2_BASE 0xB2080000
-#define SPEAR310_UART3_BASE 0xB2100000
-#define SPEAR310_UART4_BASE 0xB2180000
-#define SPEAR310_UART5_BASE 0xB2200000
-#define SPEAR310_HDLC_BASE 0xB2800000
-#define SPEAR310_RS485_0_BASE 0xB3000000
-#define SPEAR310_RS485_1_BASE 0xB3800000
-#define SPEAR310_SOC_CONFIG_BASE 0xB4000000
+#define SPEAR310_NAND_BASE UL(0x40000000)
+#define SPEAR310_FSMC_BASE UL(0x44000000)
+#define SPEAR310_UART1_BASE UL(0xB2000000)
+#define SPEAR310_UART2_BASE UL(0xB2080000)
+#define SPEAR310_UART3_BASE UL(0xB2100000)
+#define SPEAR310_UART4_BASE UL(0xB2180000)
+#define SPEAR310_UART5_BASE UL(0xB2200000)
+#define SPEAR310_HDLC_BASE UL(0xB2800000)
+#define SPEAR310_RS485_0_BASE UL(0xB3000000)
+#define SPEAR310_RS485_1_BASE UL(0xB3800000)
+#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
/* Interrupt registers offsets and masks */
#define INT_STS_MASK_REG 0x04