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authorOlof Johansson <olof@lixom.net>2015-08-21 10:15:29 -0700
committerOlof Johansson <olof@lixom.net>2015-08-21 10:15:29 -0700
commitf4be3c67ed5829462f53e225edd95029bb0793c4 (patch)
treedd42c2a7a3abed53449c09650e93eacb500f703c /arch/arm/mach-omap2
parent99650c258a4bbe7e62754c734c3888f29b59f72a (diff)
parent17cdddf0fb684f5456c1af3aa2c10aca3b68b8de (diff)
Merge tag 'tegra-for-4.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
ARM: tegra: Devicetree changes for v4.3-rc1 Enables CPU frequency scaling on Jetson TK1 and enables the GK20A GPU on Venice2 and Jetson TK1. This also enables support for the PMU hardware found on Tegra124, which among other things, can be used for performance measurements. * tag 'tegra-for-4.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree pinctrl: tegra: Only set the gpio range if needed clk: tegra: Add the DFLL as a possible parent of the cclk_g clock clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend clk: tegra: Add Tegra124 DFLL clocksource platform driver clk: tegra: Add DFLL DVCO reset control for Tegra124 clk: tegra: Introduce ability for SoC-specific reset control callbacks clk: tegra: Add functions for parsing CVB tables clk: tegra: Add closed loop support for the DFLL clk: tegra: Add library for the DFLL clock source (open-loop mode) clk: tegra: Add binding for the Tegra124 DFLL clocksource Signed-off-by: Olof Johansson <olof@lixom.net>
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