diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-23 18:36:01 -0800 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-23 18:36:01 -0800 |
commit | 93abdb7785503c269e73e811f3c7fd23a9243b14 (patch) | |
tree | 2ec2630824a9b75c8658b1e275e2032541652e63 /arch/arm/mach-omap2 | |
parent | f341535193c338b4ce4af8e32be51e6aae7f22a6 (diff) | |
parent | 099c2e9ef671519d4c7f9d49782845adc4f54a39 (diff) |
Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC non-critical fixes from Olof Johansson:
"As usual, we have a batch of fixes that weren't considered significant
enough to warrant going into the later -rcs for previous release, so
they are queued up on this branch.
A handful of these are for various DT fixups for Samsung platforms,
and a handful of other minor things.
There are also a couple of stable-marked patches for mvebu -- they
came in quite late and we decided to keep them deferred until the
first -stable release to get more coverage instead of squeezing them
into 3.13"
* tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (32 commits)
ARM: at91: smc: bug fix in sam9_smc_cs_read()
i2c: mv64xxx: Document the newly introduced Armada XP A0 compatible
i2c: mv64xxx: Fix bus hang on A0 version of the Armada XP SoCs
ARM: mvebu: Add quirk for i2c for the OpenBlocks AX3-4 board
ARM: mvebu: Add support to get the ID and the revision of a SoC
ARM: dts: msm: Fix gpio interrupt and reg length
irqchip: sirf: set IRQ_LEVEL status_flags
ARM: OMAP2+: gpmc: Move legacy GPMC width setting
ARM: OMAP2+: gpmc: Introduce gpmc_set_legacy()
ARM: OMAP2+: gpmc: Move initialization outside the gpmc_t condition
ARM: OMAP2+: board-generic: update SoC compatibility strings
Documentation: dt: OMAP: explicitly state SoC compatible strings
ARM: OMAP2+: enable AM33xx SOC EVM audio
ARM: OMAP2+: Select USB PHY for AM335x SoC
ARM: bcm2835: Fix grammar in help message
ARM: msm: trout: fix uninit var warning
ARM: dts: Use MSHC controller for eMMC memory for exynos4412-trats2
ARM: dts: Fix definition of MSHC device tree nodes for exynos4x12
ARM: dts: add clock provider for mshc node for Exynos4412 SOC
clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider
...
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/board-generic.c | 7 | ||||
-rw-r--r-- | arch/arm/mach-omap2/gpmc-nand.c | 50 |
2 files changed, 35 insertions, 22 deletions
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 8d972ff18c56..8e3daa11602b 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -78,6 +78,7 @@ MACHINE_END #ifdef CONFIG_ARCH_OMAP3 static const char *omap3_boards_compat[] __initdata = { + "ti,omap3430", "ti,omap3", NULL, }; @@ -173,6 +174,8 @@ MACHINE_END #ifdef CONFIG_ARCH_OMAP4 static const char *omap4_boards_compat[] __initdata = { + "ti,omap4460", + "ti,omap4430", "ti,omap4", NULL, }; @@ -193,6 +196,8 @@ MACHINE_END #ifdef CONFIG_SOC_OMAP5 static const char *omap5_boards_compat[] __initdata = { + "ti,omap5432", + "ti,omap5430", "ti,omap5", NULL, }; @@ -213,6 +218,7 @@ MACHINE_END #ifdef CONFIG_SOC_AM43XX static const char *am43_boards_compat[] __initdata = { + "ti,am4372", "ti,am43", NULL, }; @@ -230,6 +236,7 @@ MACHINE_END #ifdef CONFIG_SOC_DRA7XX static const char *dra7xx_boards_compat[] __initdata = { + "ti,dra7xx", "ti,dra7", NULL, }; diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 662c7fd633cc..174caecc3186 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -65,6 +65,22 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) return 1; } +/* This function will go away once the device-tree convertion is complete */ +static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data, + struct gpmc_settings *s) +{ + /* Enable RD PIN Monitoring Reg */ + if (gpmc_nand_data->dev_ready) { + s->wait_on_read = true; + s->wait_on_write = true; + } + + if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) + s->device_width = GPMC_DEVWIDTH_16BIT; + else + s->device_width = GPMC_DEVWIDTH_8BIT; +} + int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, struct gpmc_timings *gpmc_t) { @@ -98,32 +114,22 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, dev_err(dev, "Unable to set gpmc timings: %d\n", err); return err; } + } - if (gpmc_nand_data->of_node) { - gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); - } else { - /* Enable RD PIN Monitoring Reg */ - if (gpmc_nand_data->dev_ready) { - s.wait_on_read = true; - s.wait_on_write = true; - } - } - - s.device_nand = true; + if (gpmc_nand_data->of_node) + gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); + else + gpmc_set_legacy(gpmc_nand_data, &s); - if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) - s.device_width = GPMC_DEVWIDTH_16BIT; - else - s.device_width = GPMC_DEVWIDTH_8BIT; + s.device_nand = true; - err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); - if (err < 0) - goto out_free_cs; + err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); + if (err < 0) + goto out_free_cs; - err = gpmc_configure(GPMC_CONFIG_WP, 0); - if (err < 0) - goto out_free_cs; - } + err = gpmc_configure(GPMC_CONFIG_WP, 0); + if (err < 0) + goto out_free_cs; gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); |