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authorOlof Johansson <olof@lixom.net>2013-06-14 14:31:36 -0700
committerOlof Johansson <olof@lixom.net>2013-06-14 14:32:01 -0700
commit10f8902b47340fc792cf503dd3caaba410d23615 (patch)
treec81e0af4e9b3b7c2f221c74c02dea034350f8907 /arch/arm/mach-mvebu
parenteb25862dee69a0a0ba835f6ed093c75f8ed3123b (diff)
parent4f288f081bb67813d35c10d1b2fa68e863c4b188 (diff)
Merge tag 'omap-for-v3.11/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren: Omap SoC changes. Mostly improves am33xx support, and adds minimal support for am43x SoCs. * tag 'omap-for-v3.11/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: AM43x: SRAM base and size ARM: OMAP2+: AM43x: GP or HS ? ARM: OMAP2+: AM43x: early init ARM: OMAP2+: AM43x: static mapping ARM: OMAP2+: AM437x: SoC revision detection ARM: OMAP2+: AM43x: soc_is support ARM: OMAP2+: AM43x: kbuild ARM: OMAP2+: AM43x: Kconfig ARM: OMAP2+: separate out OMAP4 restart ARM: AM33XX: clk: Add clock node for EHRPWM TBCLK ARM: OMAP3: clock data: get rid of unused USB host clock aliases and dummies ARM: OMAP2+: AM33xx: Add missing reset status info to GFX hwmod + Linux 3.10-rc5 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-mvebu')
-rw-r--r--arch/arm/mach-mvebu/coherency_ll.S16
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 53e8391192cd..5476669ba905 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -32,15 +32,21 @@ ENTRY(ll_set_cpu_coherent)
/* Add CPU to SMP group - Atomic */
add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
- ldr r2, [r3]
+1:
+ ldrex r2, [r3]
orr r2, r2, r1
- str r2, [r3]
+ strex r0, r2, [r3]
+ cmp r0, #0
+ bne 1b
/* Enable coherency on CPU - Atomic */
- add r3, r0, #ARMADA_XP_CFB_CFG_REG_OFFSET
- ldr r2, [r3]
+ add r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET
+1:
+ ldrex r2, [r3]
orr r2, r2, r1
- str r2, [r3]
+ strex r0, r2, [r3]
+ cmp r0, #0
+ bne 1b
dsb