diff options
author | Eric Miao <eric.miao@marvell.com> | 2009-01-20 17:20:56 +0800 |
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committer | Eric Miao <eric.miao@marvell.com> | 2009-03-23 10:11:34 +0800 |
commit | a7a89d9621ba877ae45784cf7d000182075df9c1 (patch) | |
tree | a6baf058a43f72088750af59c3d78ee3f512a69d /arch/arm/mach-mmp/include/mach/mfp.h | |
parent | e2bb6650ef94c64723e2dd35ab92410b9477bc64 (diff) |
[ARM] pxa: add MFP support for pxa168
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Diffstat (limited to 'arch/arm/mach-mmp/include/mach/mfp.h')
-rw-r--r-- | arch/arm/mach-mmp/include/mach/mfp.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-mmp/include/mach/mfp.h new file mode 100644 index 000000000000..277ea4cd0f9f --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp.h @@ -0,0 +1,37 @@ +#ifndef __ASM_MACH_MFP_H +#define __ASM_MACH_MFP_H + +#include <plat/mfp.h> + +/* + * NOTE: the MFPR register bit definitions on PXA168 processor lines are a + * bit different from those on PXA3xx. Bit [7:10] are now reserved, which + * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits. + * + * To cope with this difference and re-use the pxa3xx mfp code as much as + * possible, we make the following compromise: + * + * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT) + * 2. DRIVE strength definitions redefined to include the reserved bit10 + * 3. Override MFP_CFG() and MFP_CFG_DRV() + * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X() + */ + +#define MFP_DRIVE_VERY_SLOW (0x0 << 13) +#define MFP_DRIVE_SLOW (0x2 << 13) +#define MFP_DRIVE_MEDIUM (0x4 << 13) +#define MFP_DRIVE_FAST (0x8 << 13) + +#undef MFP_CFG +#undef MFP_CFG_DRV +#undef MFP_CFG_LPM +#undef MFP_CFG_X +#undef MFP_CFG_DEFAULT + +#define MFP_CFG(pin, af) \ + (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM) + +#define MFP_CFG_DRV(pin, af, drv) \ + (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv) + +#endif /* __ASM_MACH_MFP_H */ |