diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-01-05 13:25:15 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-01-05 13:25:27 +0000 |
| commit | 7b9dd47136c07ffd883aff6926c7b281e4c1eea4 (patch) | |
| tree | b835312e76fe323de3e1cbbb0d15fca5a3f7ef9c /arch/arm/mach-exynos/mach-smdkv310.c | |
| parent | 2e0e943436912ffe0848ece58167edfe754edb96 (diff) | |
| parent | 0575fb754dbfc32a01f297e778533340a533ec68 (diff) | |
Merge branch 'restart' into for-linus
Conflicts:
arch/arm/mach-exynos/cpu.c
The changes to arch/arm/mach-exynos/cpu.c were moved to
mach-exynos/common.c.
Diffstat (limited to 'arch/arm/mach-exynos/mach-smdkv310.c')
| -rw-r--r-- | arch/arm/mach-exynos/mach-smdkv310.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index edc60b6108ed..5b365613b470 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c @@ -28,7 +28,6 @@ #include <plat/regs-serial.h> #include <plat/regs-srom.h> #include <plat/regs-fb-v4.h> -#include <plat/exynos4.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/fb.h> @@ -44,6 +43,8 @@ #include <mach/map.h> +#include "common.h" + /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ @@ -333,7 +334,7 @@ static void s5p_tv_setup(void) static void __init smdkv310_map_io(void) { - s5p_init_io(NULL, 0, S5P_VA_CHIPID); + exynos_init_io(NULL, 0); s3c24xx_init_clocks(24000000); s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); } @@ -380,6 +381,7 @@ MACHINE_START(SMDKV310, "SMDKV310") .init_machine = smdkv310_machine_init, .timer = &exynos4_timer, .reserve = &smdkv310_reserve, + .restart = exynos4_restart, MACHINE_END MACHINE_START(SMDKC210, "SMDKC210") @@ -390,4 +392,5 @@ MACHINE_START(SMDKC210, "SMDKC210") .handle_irq = gic_handle_irq, .init_machine = smdkv310_machine_init, .timer = &exynos4_timer, + .restart = exynos4_restart, MACHINE_END |