diff options
| author | Stephen Warren <swarren@nvidia.com> | 2013-10-28 16:56:14 -0600 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-12-04 12:25:12 -0700 |
| commit | 354935a9e804878ec64a86ad8b7f091d544dcb54 (patch) | |
| tree | 2504a5686897e5d6df49c4cbbae0c84203bc5e81 /arch/arm/include | |
| parent | cdcb5a074cd3e33e7bdb318487fde8a9e55d6159 (diff) | |
ARM: tegra: fix DEBUG_LL combined with LPAE
The DEBUG_LL UART address is mapped as an MMU section, hence, the
virtual address must be section-aligned. Sections are 1MB without LPAE
and 2MB with LPAE. Tegra's virtual address was only aligned to 1MB, and
hence the mapping was set up incorrectly with LPAE enabled, thus causing
a hang early during boot. Fix this by picking a different virtual address
that is aligned to 2MB.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/debug/tegra.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S index be6a720dd183..a7b7cedef1a6 100644 --- a/arch/arm/include/debug/tegra.S +++ b/arch/arm/include/debug/tegra.S @@ -46,10 +46,10 @@ #define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804) /* - * Must be 1MB-aligned since a 1MB mapping is used early on. + * Must be section-aligned since a section mapping is used early on. * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[]. */ -#define UART_VIRTUAL_BASE 0xfe100000 +#define UART_VIRTUAL_BASE 0xfe800000 #define checkuart(rp, rv, lhu, bit, uart) \ /* Load address of CLK_RST register */ \ |