Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: GIC: don't disable software generated interrupts
  ARM: 6472/1: vexpress ct-ca9x4: only set twd_base if local timers are being used
  ARM: arch/arm/kernel/traps.c: Convert sprintf_symbol to %pS
  ARM: arch/arm/kernel/hw_breakpoint.c: Convert WARN_ON to WARN
  ARM: 6462/1: EP93xx: Document DMA M2P API
  ARM: 6470/1: atomic64: use generic implementation for OABI configurations
  ARM: 6469/1: perf-events: squash compiler warning
  ARM: 6468/1: backtrace: fix calculation of thread stack base
  ARM: Fix DMA coherent allocator alignment
  ARM: orion5x/kirkwood/mv78xx0: fix MPP configuration corner cases
  [ARM] TS-78xxx NAND resource type should be IORESOURCE_MEM
  ARM: pxa/saar: fix the building failure caused by typo
  ARM: pxa/cm-x2xx: remove duplicate call to pxa27x_init_irq
  ARM: pxa: fix the missing definition of IRQ_BOARD_END
  ARM: mmp: fix cpuid detection on mmp2
  [ARM] Kirkwood: restrict the scope of the PCIe reset workaround
  [ARM] Kirkwood: fix timer initialization for LaCie boards
  [ARM] Kirkwood: enhance TCLK detection

1 files changed, 24 insertions, 4 deletions

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index ada6359160eb..772f95f1aecd 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -251,15 +251,16 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
 		writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 
 	/*
-	 * Set priority on all interrupts.
+	 * Set priority on all global interrupts.
 	 */
-	for (i = 0; i < max_irq; i += 4)
+	for (i = 32; i < max_irq; i += 4)
 		writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
 
 	/*
-	 * Disable all interrupts.
+	 * Disable all interrupts.  Leave the PPI and SGIs alone
+	 * as these enables are banked registers.
 	 */
-	for (i = 0; i < max_irq; i += 32)
+	for (i = 32; i < max_irq; i += 32)
 		writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
 
 	/*
@@ -277,11 +278,30 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
 
 void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
 {
+	void __iomem *dist_base;
+	int i;
+
 	if (gic_nr >= MAX_GIC_NR)
 		BUG();
 
+	dist_base = gic_data[gic_nr].dist_base;
+	BUG_ON(!dist_base);
+
 	gic_data[gic_nr].cpu_base = base;
 
+	/*
+	 * Deal with the banked PPI and SGI interrupts - disable all
+	 * PPI interrupts, ensure all SGI interrupts are enabled.
+	 */
+	writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
+	writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
+
+	/*
+	 * Set priority on PPI and SGI interrupts
+	 */
+	for (i = 0; i < 32; i += 4)
+		writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+
 	writel(0xf0, base + GIC_CPU_PRIMASK);
 	writel(1, base + GIC_CPU_CTRL);
 }