diff options
| author | Hyungwon Hwang <human.hwang@samsung.com> | 2015-06-12 21:59:10 +0900 |
|---|---|---|
| committer | Inki Dae <inki.dae@samsung.com> | 2015-06-22 21:40:13 +0900 |
| commit | 4f01e65037187581971f8b1068d4e1b1300a6562 (patch) | |
| tree | 8e0ff2f489f6216836e49dae0c0d12503897a8f6 /arch/arm/boot | |
| parent | 51d1deca9f03f8d2619d38916675a7fdc7f24730 (diff) | |
ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
The clock which was named as 'pll_clk' is actually not the clock source
of PLL in MIPI DSI. This patch fixes this disagreement.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/exynos4.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index e20cdc24c3bb..1538d7ae7b86 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -167,7 +167,7 @@ phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "pll_clk"; + clock-names = "bus_clk", "sclk_mipi"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; |