diff options
author | Arnd Bergmann <arnd@arndb.de> | 2011-10-20 18:15:30 +0200 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2011-10-20 18:15:30 +0200 |
commit | 107532920226a37e595697959b2a6a823cfa2497 (patch) | |
tree | 7d35c84ed324e6cabeed29282f1fc97994fd204b /arch/arm/boot | |
parent | 29ea35969b92a4be122a58c4aceea8c5e2c388d9 (diff) | |
parent | ecb7b0e33e048e63d1169e6fee277430c70ddf0b (diff) |
Merge branch 'tegra/devel' into next/devel
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/dts/tegra-ventana.dts | 32 | ||||
-rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 8 |
2 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts new file mode 100644 index 000000000000..9b29a623aaf1 --- /dev/null +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +/memreserve/ 0x1c000000 0x04000000; +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra2 Ventana evaluation board"; + compatible = "nvidia,ventana", "nvidia,tegra20"; + + chosen { + bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init"; + }; + + memory { + reg = < 0x00000000 0x40000000 >; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + sdhci@c8000400 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + }; + + sdhci@c8000600 { + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + support-8bit; + }; +}; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 5727595cde61..65d7e6a333eb 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -77,6 +77,14 @@ gpio-controller; }; + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra20-pinmux"; + reg = < 0x70000014 0x10 /* Tri-state registers */ + 0x70000080 0x20 /* Mux registers */ + 0x700000a0 0x14 /* Pull-up/down registers */ + 0x70000868 0xa8 >; /* Pad control registers */ + }; + serial@70006000 { compatible = "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; |