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| author | M'boumba Cedric Madianga <cedric.madianga@gmail.com> | 2017-02-01 18:19:07 +0100 |
|---|---|---|
| committer | Alexandre TORGUE <alexandre.torgue@st.com> | 2017-02-01 18:19:31 +0100 |
| commit | 51576d360305436a10d92babca37d86b18d32f46 (patch) | |
| tree | 6c33fd2f294a0fcef60fece07d50d0ad54b548fc /arch/arm/boot/dts | |
| parent | f20a406bf74f073d8b22a04eb1bf9062c3e4f848 (diff) | |
ARM: dts: stm32: Add I2C1 support for STM32F429 SoC
This patch adds I2C1 support for STM32F429 SoC
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/stm32f429.dtsi | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 3f441fbedb8f..ee0da970e8ad 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -342,6 +342,18 @@ status = "disabled"; }; + i2c1: i2c@40005400 { + compatible = "st,stm32f4-i2c"; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32F4_APB1_RESET(I2C1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + usart7: serial@40007800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007800 0x400>; @@ -714,6 +726,16 @@ <STM32F429_PB5_FUNC_TIM3_CH2>; }; }; + + i2c1_pins: i2c1@0 { + pins { + pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>, + <STM32F429_PB6_FUNC_I2C1_SCL>; + bias-disable; + drive-open-drain; + slew-rate = <3>; + }; + }; }; rcc: rcc@40023810 { |