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authorLee Jones <lee.jones@linaro.org>2014-07-22 11:28:00 +0200
committerMaxime Coquelin <maxime.coquelin@st.com>2014-10-31 09:59:07 +0100
commit45188b726e231c069a78163a24243b83fbee7d34 (patch)
tree2016052c7e2d37421b026306167b722d01808e6b /arch/arm/boot/dts
parentd436a609444b05beeced27cc30be88205c716d59 (diff)
ARM: DT: STi: STiH416: Add DT node for ST's SATA device
ARM: DT: STi: STiH416: Add DT node for ST's SATA device Cc: devicetree@vger.kernel.org Acked-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/stih416-b2020.dts4
-rw-r--r--arch/arm/boot/dts/stih416-b2020e.dts4
-rw-r--r--arch/arm/boot/dts/stih416.dtsi16
3 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
index 7ce798be5e01..5d1543babf56 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -29,5 +29,9 @@
st,pcie-tx-pol-inv;
};
};
+
+ sata0: sata@fe380000{
+ status = "okay";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index fa59224115bb..956fab8b8ffe 100644
--- a/arch/arm/boot/dts/stih416-b2020e.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
@@ -47,5 +47,9 @@
st,pcie-tx-pol-inv;
};
};
+
+ sata0: sata@fe380000{
+ status = "okay";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index a54f6832a9ac..1137bdfcca1c 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -300,5 +300,21 @@
reg-names = "sata", "pcie", "syscfg";
};
};
+
+ sata0: sata@fe380000 {
+ compatible = "st,sti-ahci";
+ reg = <0xfe380000 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
+ interrupt-names = "hostc";
+ phys = <&phy_port0 MIPHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ resets = <&powerdown STIH416_SATA0_POWERDOWN>,
+ <&softreset STIH416_SATA0_SOFTRESET>;
+ reset-names = "pwr-dwn", "sw-rst";
+ clock-names = "ahci_clk";
+ clocks = <&clk_s_a0_ls CLK_ICN_REG>;
+
+ status = "disabled";
+ };
};
};