diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2014-02-03 09:51:43 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-02-07 20:24:09 +0100 |
| commit | 7b5b2909f30a273155a72c2c7a4faac8107aeff1 (patch) | |
| tree | 6c09b24ac91cd1c36540ae69b5b91625208ca61a /arch/arm/boot/dts/sun6i-a31.dtsi | |
| parent | 3dce8324949eaa1ab4b750e8422ce78ddceb7aa4 (diff) | |
ARM: dts: sun6i: rename clock node names to clk@N
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match and
add clock-output-names to all sunxi clock nodes.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun6i-a31.dtsi | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index fc07f7089b85..d3f19951d501 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -70,17 +70,19 @@ clock-frequency = <24000000>; }; - osc32k: osc32k { + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-output-names = "osc32k"; }; - pll1: pll1@01c20000 { + pll1: clk@01c20000 { #clock-cells = <0>; compatible = "allwinner,sun6i-a31-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; pll6: clk@01c20028 { @@ -103,6 +105,7 @@ * Allwinner. */ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + clock-output-names = "cpu"; }; axi: axi@01c20050 { @@ -110,6 +113,7 @@ compatible = "allwinner,sun4i-axi-clk"; reg = <0x01c20050 0x4>; clocks = <&cpu>; + clock-output-names = "axi"; }; ahb1_mux: ahb1_mux@01c20054 { @@ -117,6 +121,7 @@ compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; + clock-output-names = "ahb1_mux"; }; ahb1: ahb1@01c20054 { @@ -124,9 +129,10 @@ compatible = "allwinner,sun4i-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb1_mux>; + clock-output-names = "ahb1"; }; - ahb1_gates: ahb1_gates@01c20060 { + ahb1_gates: clk@01c20060 { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; reg = <0x01c20060 0x8>; @@ -152,9 +158,10 @@ compatible = "allwinner,sun4i-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb1>; + clock-output-names = "apb1"; }; - apb1_gates: apb1_gates@01c20060 { + apb1_gates: clk@01c20068 { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-apb1-gates-clk"; reg = <0x01c20068 0x4>; @@ -169,6 +176,7 @@ compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; + clock-output-names = "apb2_mux"; }; apb2: apb2@01c20058 { @@ -176,9 +184,10 @@ compatible = "allwinner,sun6i-a31-apb2-div-clk"; reg = <0x01c20058 0x4>; clocks = <&apb2_mux>; + clock-output-names = "apb2"; }; - apb2_gates: apb2_gates@01c2006c { + apb2_gates: clk@01c2006c { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-apb2-gates-clk"; reg = <0x01c2006c 0x4>; |