diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2014-04-15 01:16:44 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2014-07-26 23:15:22 +0200 |
| commit | b13d2a7b43654c7f52aba9dc04f93cf7055ebc8b (patch) | |
| tree | 612405f09cfa849f3067ac412dafc9b2f5c5d952 /arch/arm/boot/dts/rk3066a.dtsi | |
| parent | 1fe69496cf463b654d2d6e1a9a10fb8d99f10831 (diff) | |
ARM: dts: rockchip: add cru nodes and update device clocks to use it
This adds a node for the clock and reset unit on rk3188 and rk3066 SoCs and
also updates the device nodes retrieve their clocks from there, instead of
the previous gate clock nodes.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3066a.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3066a.dtsi | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 4387cfd420ba..15c81d2c2d52 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3066a-cru.h> #include "rk3xxx.dtsi" #include "rk3066a-clocks.dtsi" @@ -45,7 +46,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x20038000 0x100>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates1 0>, <&clk_gates7 7>; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; clock-names = "timer", "pclk"; }; @@ -53,7 +54,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x2003a000 0x100>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates1 1>, <&clk_gates7 8>; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; clock-names = "timer", "pclk"; }; @@ -61,7 +62,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x2000e000 0x100>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates1 2>, <&clk_gates7 9>; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; clock-names = "timer", "pclk"; }; @@ -78,6 +79,15 @@ }; }; + cru: clock-controller@20000000 { + compatible = "rockchip,rk3066a-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; @@ -89,7 +99,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20034000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 9>; + clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -102,7 +112,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 10>; + clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -115,7 +125,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 11>; + clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; @@ -128,7 +138,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 12>; + clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; @@ -141,7 +151,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20084000 0x100>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 13>; + clocks = <&cru PCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; @@ -154,7 +164,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2000a000 0x100>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 15>; + clocks = <&cru PCLK_GPIO6>; gpio-controller; #gpio-cells = <2>; |