diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2020-08-16 20:07:32 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-08-25 11:19:03 +0200 |
| commit | 5a81ade1dd284a25c25b7582e94e33e5690c3da5 (patch) | |
| tree | 26dc0a2287c2ad72ff77e07fc0cdb1f19cce8e54 /arch/arm/boot/dts/r8a7742.dtsi | |
| parent | 0c77ecdcfcd35e97c677e49a8516a0b10c1e8fb7 (diff) | |
ARM: dts: r8a7742: Add CAN support
Add the definitions for can0 and can1 to the r8a7742 SoC dtsi.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Link: https://lore.kernel.org/r/20200816190732.6905-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm/boot/dts/r8a7742.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7742.dtsi | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 009827708bf4..0fc52b27ae64 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -36,6 +36,14 @@ clock-frequency = <0>; }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -951,6 +959,32 @@ status = "disabled"; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7742", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7742", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; |