diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-01-14 12:13:01 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2015-01-15 08:54:31 +0900 |
| commit | f4c6d004eac803cf90452c94ec5f3210c2d44c01 (patch) | |
| tree | 41d86f71f6736b3f12520ed0512175b076c61d28 /arch/arm/boot/dts/r8a7740.dtsi | |
| parent | 35dd549cb300e346e2f2ec1f12dd9cd245b3276b (diff) | |
ARM: shmobile: r8a7740 dtsi: Add memory-controller node
Add a device node for the DDR3 Bus State Controller (DBSC3).
The DBSC3 is located in the A4S PM domain, which must not be powered
down, else the system will crash.
This has no visible effect for now, as A4S was never turned off anyway
because its child PM domain A3SM contains the CPU core.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7740.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7740.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 52f2cf4b84d3..8a092605d641 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -37,6 +37,12 @@ <0xc2000000 0x1000>; }; + dbsc3: memory-controller@fe400000 { + compatible = "renesas,dbsc3-r8a7740"; + reg = <0xfe400000 0x400>; + power-domains = <&pd_a4s>; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |