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authorKevin Hilman <khilman@linaro.org>2013-10-14 13:52:59 -0700
committerKevin Hilman <khilman@linaro.org>2013-10-14 13:53:12 -0700
commit7a093c74c7a81bd441d78cb4c6c6260284908bc3 (patch)
tree6c075e71658fa52125223b4ae8bb9d6a8ee8e5cd /arch/arm/boot/dts/r8a73a4.dtsi
parent0398436522b5deff4c1729ac3b47e4a2280e3ee7 (diff)
parent73c79afa61cdee2553461ee714bb4716372bdd55 (diff)
Merge branch 'renesas/dt2' into next/dt
From Simon Horman: * renesas/dt2: (21 commits) ARM: shmobile: bockw: fixup ether node naming ARM: shmobile: r8a7779: add irqpin default status on DTSI ARM: shmobile: marzen: fixup SMSC IRQ number on DTS ARM: shmobile: bockw: add SMSC support on DTS ARM: shmobile: r8a7778: add renesas_intc_irqpin support on DTSI ARM: shmobile: r8a7791 SMP device tree node ARM: shmobile: r8a7791 Arch timer device tree node ARM: shmobile: r8a7791 IRQC device tree node ARM: shmobile: armadillo800eva-reference: add SDHI and MMCIF interfaces ARM: shmobile: armadillo-reference: Add PWM backlight node to DT ARM: shmobile: r8a73a4: add a DT node for the DMAC ARM: shmobile: r8a7790: add I2C DT nodes ARM: shmobile: only enable used I2C interfaces in DT on all Renesas boards ARM: shmobile: r8a7778: add usb phy power control function ARM: shmobile: r8a7778: add USBHS clock ARM: shmobile: r8a7791 CMT support ARM: shmobile: r8a7791 SCIF support ARM: shmobile: Initial r8a7791 SoC support ARM: shmobile: r8a7778: add SSI/SRU clock support ARM: shmobile: r8a7790: Add DU and LVDS clocks ... Signed-off-by: Kevin Hilman <khilman@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/r8a73a4.dtsi')
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi52
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 6c26caa880f2..8c81a0c21178 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -78,6 +78,49 @@
<0 56 4>, <0 57 4>;
};
+ dmac: dma-multiplexer@0 {
+ compatible = "renesas,shdma-mux";
+ #dma-cells = <1>;
+ dma-channels = <20>;
+ dma-requests = <256>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dma0: dma-controller@e6700020 {
+ compatible = "renesas,shdma-r8a73a4";
+ reg = <0 0xe6700020 0 0x89e0>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 220 4
+ 0 200 4
+ 0 201 4
+ 0 202 4
+ 0 203 4
+ 0 204 4
+ 0 205 4
+ 0 206 4
+ 0 207 4
+ 0 208 4
+ 0 209 4
+ 0 210 4
+ 0 211 4
+ 0 212 4
+ 0 213 4
+ 0 214 4
+ 0 215 4
+ 0 216 4
+ 0 217 4
+ 0 218 4
+ 0 219 4>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19";
+ };
+ };
+
thermal@e61f0000 {
compatible = "renesas,rcar-thermal";
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
@@ -93,6 +136,7 @@
reg = <0 0xe6500000 0 0x428>;
interrupt-parent = <&gic>;
interrupts = <0 174 0x4>;
+ status = "disabled";
};
i2c1: i2c@e6510000 {
@@ -102,6 +146,7 @@
reg = <0 0xe6510000 0 0x428>;
interrupt-parent = <&gic>;
interrupts = <0 175 0x4>;
+ status = "disabled";
};
i2c2: i2c@e6520000 {
@@ -111,6 +156,7 @@
reg = <0 0xe6520000 0 0x428>;
interrupt-parent = <&gic>;
interrupts = <0 176 0x4>;
+ status = "disabled";
};
i2c3: i2c@e6530000 {
@@ -120,6 +166,7 @@
reg = <0 0xe6530000 0 0x428>;
interrupt-parent = <&gic>;
interrupts = <0 177 0x4>;
+ status = "disabled";
};
i2c4: i2c@e6540000 {
@@ -129,6 +176,7 @@
reg = <0 0xe6540000 0 0x428>;
interrupt-parent = <&gic>;
interrupts = <0 178 0x4>;
+ status = "disabled";
};
i2c5: i2c@e60b0000 {
@@ -138,6 +186,7 @@
reg = <0 0xe60b0000 0 0x428>;
interrupt-parent = <&gic>;
interrupts = <0 179 0x4>;
+ status = "disabled";
};
i2c6: i2c@e6550000 {
@@ -147,6 +196,7 @@
reg = <0 0xe6550000 0 0x428>;
interrupt-parent = <&gic>;
interrupts = <0 184 0x4>;
+ status = "disabled";
};
i2c7: i2c@e6560000 {
@@ -156,6 +206,7 @@
reg = <0 0xe6560000 0 0x428>;
interrupt-parent = <&gic>;
interrupts = <0 185 0x4>;
+ status = "disabled";
};
i2c8: i2c@e6570000 {
@@ -165,6 +216,7 @@
reg = <0 0xe6570000 0 0x428>;
interrupt-parent = <&gic>;
interrupts = <0 173 0x4>;
+ status = "disabled";
};
mmcif0: mmcif@ee200000 {