diff options
| author | Marek Vasut <marex@denx.de> | 2014-04-21 22:56:49 +0200 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@freescale.com> | 2014-05-16 23:02:02 +0800 |
| commit | 9d4ebb36a6823c64a8091f293dd5131857e596ec (patch) | |
| tree | 60575e0f7a3e9fdf189a4c4dd20dc2fc1fd153f1 /arch/arm/boot/dts/imx6qdl-sabresd.dtsi | |
| parent | fed687c526a4e93a9605f779537bf654cda1a36f (diff) | |
ARM: dts: imx6qdl-sabresd: Add PCIe support
Add support for the PCI express bus available on MX6 SabreSDP.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabresd.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 7c141f3fea63..dbbd35b89985 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -389,6 +389,13 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 @@ -473,6 +480,14 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + power-on-gpio = <&gpio3 19 0>; + reset-gpio = <&gpio7 12 0>; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; |