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authorOlof Johansson <olof@lixom.net>2014-07-19 12:16:02 -0700
committerOlof Johansson <olof@lixom.net>2014-07-19 12:16:34 -0700
commit730346236af3fcd3324dbc26e4fa13955c59fa7e (patch)
tree8bdc0ac70d36636a26e2284670aee5f15b930831 /arch/arm/boot/dts/dra7xx-clocks.dtsi
parent1409f3fd5bdb548b0e11a109baa1087680b60c5a (diff)
parent8fe9346b945d76ddb3f08c00e34d701174c62fa0 (diff)
Merge tag 'zynq-dt-for-3.17' of git://git.xilinx.com/linux-xlnx into next/dt
Merge "Xilinx Zynq changes for v3.17" from Michal Simek: arm: Xilinx Zynq dt patches for v3.17 - Document and use new cadence serial binding * tag 'zynq-dt-for-3.17' of git://git.xilinx.com/linux-xlnx: ARM: zynq: DT: Migrate UART to Cadence binding tty: cadence: Document DT binding + Linux 3.16-rc5 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/dra7xx-clocks.dtsi')
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi10
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index b987c4347911..2c05b3f017fa 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -673,10 +673,12 @@
l3_iclk_div: l3_iclk_div {
#clock-cells = <0>;
- compatible = "fixed-factor-clock";
+ compatible = "ti,divider-clock";
+ ti,max-div = <2>;
+ ti,bit-shift = <4>;
+ reg = <0x0100>;
clocks = <&dpll_core_h12x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
+ ti,index-power-of-two;
};
l4_root_clk_div: l4_root_clk_div {
@@ -684,7 +686,7 @@
compatible = "fixed-factor-clock";
clocks = <&l3_iclk_div>;
clock-mult = <1>;
- clock-div = <1>;
+ clock-div = <2>;
};
video1_clk2_div: video1_clk2_div {