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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2012-05-14 10:19:22 +1000 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2012-05-14 10:19:22 +1000 |
| commit | 8b6ee04067310a6397476f05f06e52dabd8b0bb6 (patch) | |
| tree | 022a153b777a9e38f49d46e4fb8f1e6747d4a5f4 /arch/arm/Kconfig | |
| parent | b48d441a8ab8a89bd32a3a981a05b8a26905dfc7 (diff) | |
| parent | 7c0482e3d055e5de056d3c693b821e39205b99ae (diff) | |
Merge branch 'merge' into next
We want the irq fixes from the "merge" branch.
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cf006d40342c..36586dba6fa6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1186,6 +1186,15 @@ if !MMU source "arch/arm/Kconfig-nommu" endif +config ARM_ERRATA_326103 + bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" + depends on CPU_V6 + help + Executing a SWP instruction to read-only memory does not set bit 11 + of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to + treat the access as a read, preventing a COW from occurring and + causing the faulting task to livelock. + config ARM_ERRATA_411920 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" depends on CPU_V6 || CPU_V6K |