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| author | Thomas Gleixner <tglx@linutronix.de> | 2018-01-27 15:35:29 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-01-27 15:35:29 +0100 |
| commit | 303c146df1c4574db3495d9acc5c440dd46c6b0f (patch) | |
| tree | fbcea289aea24da8a44c7677a776988bb3c8bcbe /arch/arc/boot/dts/axc003_idu.dtsi | |
| parent | b1a31a5f5f27ff8aba42b545a1c721941f735107 (diff) | |
| parent | d5421ea43d30701e03cadc56a38854c36a8b4433 (diff) | |
Merge branch 'timers/urgent' into timers/core
Pick up urgent bug fix and resolve the conflict.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arc/boot/dts/axc003_idu.dtsi')
| -rw-r--r-- | arch/arc/boot/dts/axc003_idu.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi index 63954a8b0100..69ff4895f2ba 100644 --- a/arch/arc/boot/dts/axc003_idu.dtsi +++ b/arch/arc/boot/dts/axc003_idu.dtsi @@ -35,6 +35,14 @@ reg = <0x80 0x10>, <0x100 0x10>; #clock-cells = <0>; clocks = <&input_clk>; + + /* + * Set initial core pll output frequency to 100MHz. + * It will be applied at the core pll driver probing + * on early boot. + */ + assigned-clocks = <&core_clk>; + assigned-clock-rates = <100000000>; }; core_intc: archs-intc@cpu { |