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authorDavid S. Miller <davem@davemloft.net>2015-10-30 12:21:57 +0900
committerDavid S. Miller <davem@davemloft.net>2015-10-30 12:21:57 +0900
commit65bdc43d2220bc97af037c87aba2407b46f13c2a (patch)
tree7b6bca0cfcf606f47d9b998cbc44cbc9b75b2729 /arch/alpha/defconfig
parentb7af1472afa2228bd9fe8b4cea3b003b4027d72d (diff)
parent6ccbe6b248ef8cc31477a388ea9841b56030bea9 (diff)
Merge branch 'xgene_txrx_delay'
Iyappan Subramanian says: ==================== drivers: xgene: Add support RGMII TX/RX delay configuration X-Gene RGMII ethernet controller has a RGMII bridge that performs the task of converting the RGMII signal {RX_CLK,RX_CTL, RX_DATA[3:0]} from PHY to GMII signal {RX_DV,RX_ER,RX_DATA[7:0]} and vice versa. This RGMII bridge has a provision to internally delay the input RX_CLK and the output TX_CLK using configuration registers. This will help in maintain the CLK-CTL delay relationship in various operating conditions. This patch adds support RGMII TX/RX delay configuration. ==================== Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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