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authorYijing Wang <wangyijing@huawei.com>2013-09-09 21:13:04 +0800
committerBjorn Helgaas <bhelgaas@google.com>2013-09-24 12:10:04 -0600
commit503275bf371fbab01a14f2e9fd1ac7aa20c81645 (patch)
tree295daeca82f990fce2400440234526af6b1bb264 /Makefile
parentf1c66c4678ad223bda0dcd261e4048f009234f85 (diff)
tile/PCI: use cached pci_dev->pcie_mpss to simplify code
The PCI core caches the "PCIe Max Payload Size Supported" in pci_dev->pcie_mpss, so use that instead of pcie_capability_read_dword(). Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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