diff options
| author | Huang Shijie <b32955@freescale.com> | 2013-08-16 10:10:09 +0800 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2013-08-30 21:38:45 +0100 |
| commit | ed202940335e3f9930509025e3d75721e564baca (patch) | |
| tree | 0fa28d773eb6bc31981656afb3e133c150bfb3a7 /Documentation | |
| parent | f720e7ce510bf79f029be45ce200ccfce5551280 (diff) | |
mtd: update the ABI document about the ecc step size
We add a new sys node for ecc step size. So update the ABI document about it.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
[Brian: edited description, modified 'ecc_strength']
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-class-mtd | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/Documentation/ABI/testing/sysfs-class-mtd b/Documentation/ABI/testing/sysfs-class-mtd index 3105644b3bfc..bfd119ace6ad 100644 --- a/Documentation/ABI/testing/sysfs-class-mtd +++ b/Documentation/ABI/testing/sysfs-class-mtd @@ -128,9 +128,8 @@ KernelVersion: 3.4 Contact: linux-mtd@lists.infradead.org Description: Maximum number of bit errors that the device is capable of - correcting within each region covering an ecc step. This will - always be a non-negative integer. Note that some devices will - have multiple ecc steps within each writesize region. + correcting within each region covering an ECC step (see + ecc_step_size). This will always be a non-negative integer. In the case of devices lacking any ECC capability, it is 0. @@ -173,3 +172,15 @@ Description: This is generally applicable only to NAND flash devices with ECC capability. It is ignored on devices lacking ECC capability; i.e., devices for which ecc_strength is zero. + +What: /sys/class/mtd/mtdX/ecc_step_size +Date: May 2013 +KernelVersion: 3.10 +Contact: linux-mtd@lists.infradead.org +Description: + The size of a single region covered by ECC, known as the ECC + step. Devices may have several equally sized ECC steps within + each writesize region. + + It will always be a non-negative integer. In the case of + devices lacking any ECC capability, it is 0. |