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authorWan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>2020-05-05 21:06:17 +0800
committerMark Brown <broonie@kernel.org>2020-05-05 15:08:02 +0100
commitc48e0c533e72ca264ac914addccab8a328806ed3 (patch)
treea614a610df92d50ddfc8e8fcf2686070a47a4d1a /Documentation
parent3812a081d2fcc297d039c4ffafa7778d75abcbe2 (diff)
spi: dw-apb-ssi: Add Intel Keem Bay support
Document Intel Keem Bay SPI controller DT bindings. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Link: https://lore.kernel.org/r/20200505130618.554-7-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt3
1 files changed, 2 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index 2ead46b633ea..7a4702edf896 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -2,7 +2,8 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
Required properties:
- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
- "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a"
+ "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" or
+ "intel,keembay-ssi"
- reg : The register base for the controller. For "mscc,<soc>-spi", a second
register set is required (named ICPU_CFG:SPI_MST)
- interrupts : One interrupt, used by the controller.