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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-07-10 10:10:02 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-07-10 10:10:02 -0700 |
| commit | b247759642cc96a75122907cc898b4c43b4f86ce (patch) | |
| tree | 568e6ab08f2b986ff0b1ef80318c6c56c5d2ef42 /Documentation | |
| parent | 61e312914cc82c085c945f88e5a53d507dd7d0d4 (diff) | |
| parent | 5b879d78bc0818aa710f5d4d9abbfc2aca075cc3 (diff) | |
Merge branch 'parisc-for-3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull parisc updates from Helge Deller:
"The PA-RISC updates for v3.11 include a gcc miscompilation fix,
gzip-compressed vmlinuz support, a fix in the PCI code for ATI FireGL
support on c8000 machines, a fix to prevent that %sr1 is being
clobbered and a few smaller optimizations and documentation updates"
* 'parisc-for-3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
parisc: Fix gcc miscompilation in pa_memcpy()
parisc: Ensure volatile space register %sr1 is not clobbered
parisc: optimize mtsp(0,sr) inline assembly
parisc: switch to gzip-compressed vmlinuz kernel
parisc: document the shadow registers
parisc: more capabilities info in /proc/cpuinfo
parisc: fix LMMIO mismatch between PAT length and MASK register
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/parisc/registers | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/parisc/registers b/Documentation/parisc/registers index dd3caddd1ad9..10c7d1730f5d 100644 --- a/Documentation/parisc/registers +++ b/Documentation/parisc/registers @@ -78,6 +78,14 @@ Shadow Registers used by interruption handler code TOC enable bit 1 ========================================================================= + +The PA-RISC architecture defines 7 registers as "shadow registers". +Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce +the state save and restore time by eliminating the need for general register +(GR) saves and restores in interruption handlers. +Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25. + +========================================================================= Register usage notes, originally from John Marvin, with some additional notes from Randolph Chung. |