diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2013-12-24 21:26:17 +0800 |
|---|---|---|
| committer | Emilio López <emilio@elopez.com.ar> | 2013-12-28 17:14:21 -0300 |
| commit | 6f86341726cbec1921e925fd54a10c5b58e6f9f1 (patch) | |
| tree | ec7de73187cf68dd890e8e62dcab535e4434e052 /Documentation | |
| parent | 76192dc8873f724361c1bf8a90b37abc7dfed7ad (diff) | |
clk: sunxi: Allwinner A20 output clock support
This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/sunxi.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 46d8433b2a8c..c2cb7621ad2d 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -36,6 +36,7 @@ Required properties: "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks + "allwinner,sun7i-a20-out-clk" - for the external output clocks Required properties for all clocks: - reg : shall be the control register address for the clock. |