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authorJeffrey Hugo <jeffrey.l.hugo@gmail.com>2019-05-30 09:00:23 -0700
committerRob Clark <robdclark@chromium.org>2019-06-18 13:56:42 -0700
commit590714e5a3704c7db21a4f82932d3f2699edb35c (patch)
tree0d2ee971bb6a706e4f6761d0d70d35748f6bd2ae /Documentation
parentfc19cbb785d7bbd1a1af26229b5240a3ab332744 (diff)
dt-bindings: msm/dsi: Add 10nm phy for msm8998 compatible
The DSI phy on MSM8998 is a 10nm design like SDM845, however it has some slightly different quirks which need to be handled by drivers. Provide a separate compatible to assist in handling the specifics. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/display/msm/dsi.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index 9ae946942720..af95586c898f 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -88,6 +88,7 @@ Required properties:
* "qcom,dsi-phy-28nm-8960"
* "qcom,dsi-phy-14nm"
* "qcom,dsi-phy-10nm"
+ * "qcom,dsi-phy-10nm-8998"
- reg: Physical base address and length of the registers of PLL, PHY. Some
revisions require the PHY regulator base address, whereas others require the
PHY lane base address. See below for each PHY revision.