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authorJassi Brar <jaswinder.singh@linaro.org>2019-10-14 22:31:57 -0500
committerVinod Koul <vkoul@kernel.org>2019-10-18 13:32:18 +0530
commit3708f89b33cc2aef5e121221704c1f833ca712c4 (patch)
tree32fb7d8b378ba74e645ccfc5f05bf47013dc278d /Documentation
parent6c3214e698e49da9b694cdda86332527260cf119 (diff)
dt-bindings: milbeaut-m10v-xdmac: Add Socionext Milbeaut XDMAC bindings
Document the devicetree bindings for Socionext Milbeaut XDMAC controller. Controller only supports Mem->Mem transfers. Number of physical channels are determined by the number of irqs registered. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Link: https://lore.kernel.org/r/20191015033157.14656-1-jassisinghbrar@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/dma/milbeaut-m10v-xdmac.txt24
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diff --git a/Documentation/devicetree/bindings/dma/milbeaut-m10v-xdmac.txt b/Documentation/devicetree/bindings/dma/milbeaut-m10v-xdmac.txt
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+* Milbeaut AXI DMA Controller
+
+Milbeaut AXI DMA controller has only memory to memory transfer capability.
+
+* DMA controller
+
+Required property:
+- compatible: Should be "socionext,milbeaut-m10v-xdmac"
+- reg: Should contain DMA registers location and length.
+- interrupts: Should contain all of the per-channel DMA interrupts.
+ Number of channels is configurable - 2, 4 or 8, so
+ the number of interrupts specified should be {2,4,8}.
+- #dma-cells: Should be 1.
+
+Example:
+ xdmac0: dma-controller@1c250000 {
+ compatible = "socionext,milbeaut-m10v-xdmac";
+ reg = <0x1c250000 0x1000>;
+ interrupts = <0 17 0x4>,
+ <0 18 0x4>,
+ <0 19 0x4>,
+ <0 20 0x4>;
+ #dma-cells = <1>;
+ };