diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2014-08-05 10:25:55 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2014-08-18 19:47:03 +0100 |
| commit | a3a80544acb3dfa97d43b8eee1332fe1fca7fe51 (patch) | |
| tree | 3ca111e74a6addb43b403bd43cfb73bc0b3aab13 /Documentation/xtensa | |
| parent | 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9 (diff) | |
arm64: fix typo in I-cache policy detection
This removes an unfortunately placed semi-colon resulting in all instruction
caches being classified as AIVIVT.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/xtensa')
0 files changed, 0 insertions, 0 deletions