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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-10-12 10:53:32 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-10-12 10:53:32 -0700 |
| commit | 64743e652cea9d6df4264caaa1d7f95273024afb (patch) | |
| tree | 94a3cc54ad5986c201b6ce1e6cff57686d29ce68 /Documentation/trace/events-power.rst | |
| parent | f94ab231136c53ee26b1ddda76b29218018834ff (diff) | |
| parent | 29b6bd41ee24f69a85666b9f68d500b382d408fd (diff) | |
Merge tag 'x86_cache_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cache resource control updates from Borislav Petkov:
- Misc cleanups to the resctrl code in preparation for the ARM side
(James Morse)
- Add support for controlling per-thread memory bandwidth throttling
delay values on hw which supports it (Fenghua Yu)
* tag 'x86_cache_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/resctrl: Enable user to view thread or core throttling mode
x86/resctrl: Enumerate per-thread MBA controls
cacheinfo: Move resctrl's get_cache_id() to the cacheinfo header file
x86/resctrl: Add struct rdt_cache::arch_has_{sparse, empty}_bitmaps
x86/resctrl: Merge AMD/Intel parse_bw() calls
x86/resctrl: Add struct rdt_membw::arch_needs_linear to explain AMD/Intel MBA difference
x86/resctrl: Use is_closid_match() in more places
x86/resctrl: Include pid.h
x86/resctrl: Use container_of() in delayed_work handlers
x86/resctrl: Fix stale comment
x86/resctrl: Remove struct rdt_membw::max_delay
x86/resctrl: Remove unused struct mbm_state::chunks_bw
Diffstat (limited to 'Documentation/trace/events-power.rst')
0 files changed, 0 insertions, 0 deletions