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| author | Icenowy Zheng <icenowy@aosc.io> | 2017-07-23 18:27:45 +0800 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2017-08-04 12:05:33 +0800 |
| commit | 913c3d85b4b562e38242765baa95113c8c7f1c14 (patch) | |
| tree | 1a0d0326366d15eb0bd06b8ba60de24ea4277f2c /Documentation/networking/LICENSE.qlge | |
| parent | 48d5eb619c15847aba6757deb5c2c8badca2aece (diff) | |
clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
can be adjusted by changing the frequency of the PLL_CPUX clock.
Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
clock can be adjusted when adjusting the CPUX clock.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'Documentation/networking/LICENSE.qlge')
0 files changed, 0 insertions, 0 deletions