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| author | David S. Miller <davem@davemloft.net> | 2014-03-24 14:45:12 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-03-24 14:45:12 -0400 |
| commit | cb3042d609e30e6144024801c89be3925106752b (patch) | |
| tree | 269c25b05aa778a030310f1656c501fd3d41c823 /Documentation/magic-number.txt | |
| parent | 151b628f104566a450125a6a0f6775a35bde58d6 (diff) | |
sparc64: Make sure %pil interrupts are enabled during hypervisor yield.
In arch_cpu_idle() we must enable %pil based interrupts before
potentially invoking the hypervisor cpu yield call.
As per the Hypervisor API documentation for cpu_yield:
Interrupts which are blocked by some mechanism other that
pstate.ie (for example %pil) are not guaranteed to cause
a return from this service.
It seems that only first generation Niagara chips are hit by this
bug. My best guess is that later chips implement this in hardware
and wake up anyways from %pil events, whereas in first generation
chips the yield is implemented completely in hypervisor code and
requires %pil to be enabled in order to wake properly from this
call.
Fixes: 87fa05aeb3a5 ("sparc: Use generic idle loop")
Reported-by: Fabio M. Di Nitto <fabbione@fabbione.net>
Reported-by: Jan Engelhardt <jengelh@inai.de>
Tested-by: Jan Engelhardt <jengelh@inai.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/magic-number.txt')
0 files changed, 0 insertions, 0 deletions