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| author | Min Li <min.li.xe@renesas.com> | 2020-07-14 13:15:20 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-07-17 10:25:21 -0700 |
| commit | 56a1c778c7663a3068a59b4cb8c8fd27506b3eca (patch) | |
| tree | 8ee84209b8b69e97200cb0097e9508526f184b7f /Documentation/driver-api | |
| parent | 473309fb8372365ad211f425bca760af800e10a7 (diff) | |
docs: ptp.rst: add support for Renesas (IDT) ClockMatrix
Add below to “Ancillary clock features” section
- Low Pass Filter (LPF) access from user space
Add below to list of “Supported hardware” section
+ Renesas (IDT) ClockMatrix™
Signed-off-by: Min Li <min.li.xe@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/driver-api')
| -rw-r--r-- | Documentation/driver-api/ptp.rst | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/driver-api/ptp.rst b/Documentation/driver-api/ptp.rst index a15192e32347..664838ae7776 100644 --- a/Documentation/driver-api/ptp.rst +++ b/Documentation/driver-api/ptp.rst @@ -23,6 +23,7 @@ PTP hardware clock infrastructure for Linux + Ancillary clock features - Time stamp external events - Period output signals configurable from user space + - Low Pass Filter (LPF) access from user space - Synchronization of the Linux system time via the PPS subsystem PTP hardware clock kernel API @@ -94,3 +95,14 @@ Supported hardware - Auxiliary Slave/Master Mode Snapshot (optional interrupt) - Target Time (optional interrupt) + + * Renesas (IDT) ClockMatrix™ + + - Up to 4 independent PHC channels + - Integrated low pass filter (LPF), access via .adjPhase (compliant to ITU-T G.8273.2) + - Programmable output periodic signals + - Programmable inputs can time stamp external triggers + - Driver and/or hardware configuration through firmware (idtcm.bin) + - LPF settings (bandwidth, phase limiting, automatic holdover, physical layer assist (per ITU-T G.8273.2)) + - Programmable output PTP clocks, any frequency up to 1GHz (to other PHY/MAC time stampers, refclk to ASSPs/SoCs/FPGAs) + - Lock to GNSS input, automatic switching between GNSS and user-space PHC control (optional) |