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authorMatthias Kaehlcke <mka@chromium.org>2018-07-31 11:59:13 -0700
committerEduardo Valentin <edubezval@gmail.com>2018-08-24 15:57:26 -0700
commit7fd5257f11445e35257a80d186a1da0e9795068f (patch)
tree9b02446b6c1da4f2c58391c47c04c5f734ce7562 /Documentation/devicetree/bindings/thermal
parent2ad0d52699700a91660a406a4046017a2d7f246a (diff)
dt-bindings: thermal: qcom-spmi-temp-alarm: Fix documentation of 'reg'
The documentation claims that the 'reg' property consists of two values, the SPMI address and the length of the controller's registers. However the SPMI bus to which it is added specifies "#size-cells = <0>;". Remove the controller register length from the documentation of the field and the example. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Diffstat (limited to 'Documentation/devicetree/bindings/thermal')
-rw-r--r--Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt5
1 files changed, 2 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt b/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt
index 290ec06fa33a..86fb41fe772f 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt
+++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt
@@ -6,8 +6,7 @@ interrupt signal and status register to identify high PMIC die temperature.
Required properties:
- compatible: Should contain "qcom,spmi-temp-alarm".
-- reg: Specifies the SPMI address and length of the controller's
- registers.
+- reg: Specifies the SPMI address.
- interrupts: PMIC temperature alarm interrupt.
- #thermal-sensor-cells: Should be 0. See thermal.txt for a description.
@@ -20,7 +19,7 @@ Example:
pm8941_temp: thermal-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
- reg = <0x2400 0x100>;
+ reg = <0x2400>;
interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
#thermal-sensor-cells = <0>;