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authorArnd Bergmann <arnd@arndb.de>2019-09-04 17:28:46 +0200
committerArnd Bergmann <arnd@arndb.de>2019-09-04 17:28:47 +0200
commit49826a68b5c503bd338d84e0150e06bd5b4f43fa (patch)
tree4a589ef43f5673aea1c0cf4b202805d92feecb97 /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt
parent65ab0dba3c8dcdfbb5850c451cccc811499d32ba (diff)
parent7109d817db2e020379d0f245300b8ffe651c5c04 (diff)
Merge tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu into arm/late
mvebu dt64 for 5.4 (part 2) Add support for Turris Mox board (Armada 3720 SoC based) * tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu: (53 commits) arm64: dts: marvell: add DTS for Turris Mox dt-bindings: marvell: document Turris Mox compatible arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl arm64: dts: marvell: Add cpu clock node on Armada 7K/8K arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes arm64: dts: marvell: Add CP110 COMPHY clocks arm64: dts: marvell: armada-37xx: add mailbox node dt-bindings: gpio: Document GPIOs via Moxtet bus drivers: gpio: Add support for GPIOs over Moxtet bus bus: moxtet: Add sysfs and debugfs documentation dt-bindings: bus: Document moxtet bus binding bus: Add support for Moxtet bus reset: Add support for resets provided by SCMI firmware: arm_scmi: Add RESET protocol in SCMI v2.0 dt-bindings: arm: Extend SCMI to support new reset protocol firmware: arm_scmi: Make use SCMI v2.0 fastchannel for performance protocol firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels ... Link: https://lore.kernel.org/r/87h85two0r.fsf@FE-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt')
-rw-r--r--Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt13
1 files changed, 12 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt
index d7afaff5faff..05ec2a838c54 100644
--- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt
@@ -18,7 +18,8 @@ Required properties:
- reg : offset and length of the device registers.
- bus-frequency : the clock frequency for QUICC Engine.
- fsl,qe-num-riscs: define how many RISC engines the QE has.
-- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the
+- fsl,qe-snums: This property has to be specified as '/bits/ 8' value,
+ defining the array of serial number (SNUM) values for the virtual
threads.
Optional properties:
@@ -34,6 +35,11 @@ Recommended properties
- brg-frequency : the internal clock source frequency for baud-rate
generators in Hz.
+Deprecated properties
+- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use
+ for the threads. Use fsl,qe-snums instead to not only specify the
+ number of snums, but also their values.
+
Example:
qe@e0100000 {
#address-cells = <1>;
@@ -44,6 +50,11 @@ Example:
reg = <e0100000 480>;
brg-frequency = <0>;
bus-frequency = <179A7B00>;
+ fsl,qe-snums = /bits/ 8 <
+ 0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D
+ 0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89
+ 0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9
+ 0xD8 0xD9 0xE8 0xE9>;
}
* Multi-User RAM (MURAM)