diff options
| author | Alexandre Belloni <alexandre.belloni@free-electrons.com> | 2018-01-16 11:12:34 +0100 |
|---|---|---|
| committer | Sebastian Reichel <sre@kernel.org> | 2018-02-12 11:23:46 +0100 |
| commit | 5e195f120138a7ab8245a5e64296c16f8e48527f (patch) | |
| tree | fc3115e13add02d9e9081afb698ca1b1498fae72 /Documentation/devicetree/bindings/power | |
| parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) | |
dt-bindings: power: reset: Document ocelot-reset binding
Add binding documentation for the Microsemi Ocelot reset block.
Cc: devicetree@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Diffstat (limited to 'Documentation/devicetree/bindings/power')
| -rw-r--r-- | Documentation/devicetree/bindings/power/reset/ocelot-reset.txt | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt new file mode 100644 index 000000000000..1b4213eb3473 --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -0,0 +1,14 @@ +Microsemi Ocelot reset controller + +The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the +SoC MIPS core. + +Required Properties: + - compatible: "mscc,ocelot-chip-reset" + +Example: + reset@1070008 { + compatible = "mscc,ocelot-chip-reset"; + reg = <0x1070008 0x4>; + }; + |